Virtual addressing to data/instruction caches has advantages relative to physical addressing techniques. Software using virtual addresses obtains advantages associated with relocation, which is especially useful in multiprocessing environments. Moreover, programs can be executed that require memory larger than the physical memory present in the machine by caching data/instructions on a larger data store, such as a hard drive.
Typically, however, hardware extracts a latency penalty to support virtual addressing. A virtual address generated by software and issued from a central processing unit (CPU) or input/output (I/O) device must first be passed to a memory management unit (MMU) that converts the virtual address to a physical address using a translation buffer. This physical address is then passed to the physically addressed cache. The serial nature of these operations, i.e., virtual-to-physical address translation followed by physical addressing, increases the time before information can be received back from the cache or the determination of a cache-miss, in which the desired information is not present in the cache.
Virtual caches or caches that support virtual addressing have been developed to remove the hardware latency commonly associated with virtual addressing. Virtual addresses from the CPU are passed to the MMU and the virtual cache in parallel. The MMU provides authorization/access control information for the cache addressing and the physical address, and the virtual cache returns the addressed information, or alternatively a cache-miss. In the cache-miss situation, the MMU's physical address is used.
A common issue that arises with virtual caches is aliasing, i.e., the mapping of multiple virtual addresses to the same physical address in memory. This can lead to problems in write-back data caches where software updates data in the cache so that the only place where the data is valid is in the cache until it is returned back to main memory. The existence of aliased virtual addresses in the virtual cache leads to portions of the virtual cache that are incoherent with respect to each other. When the data is returned, main memory may include only part of the changes originally made by the CPU to the cache.
Hardware confronts the issue of virtual address aliasing one of two ways. Either it is supported with additional hardware or simply outlawed, i.e., not supported, which limits its software compatibility.
The hardware support for virtual address aliasing usually takes the form of back-maps. This is a tag store that is in parallel with the cache. The back-map indicates on cache-misses whether the accessed block already exists in the cache, but under an aliased address. Backmaps have the advantage of being out of the critical path as they are only consulted on cache-misses. Thus, they do not increase latency. The drawback, however, is the additional tag store that must be present for every cache location. Consequently, many hardware systems do not provide back-maps for virtual address aliasing.